1. Field of the Invention
The present invention relates to semiconductor devices, and particularly to a technique that can simultaneously solve problems related to the element isolation, i.e. formation of voids, impurity diffusion from a doped insulator into the semiconductor substrate etc., and thickness reduction of the gate insulating film caused by silicon nitride film.
2. Description of the Background Art
Element isolation having isolation regions are necessary in order to eliminate electrical interference among elements in semiconductor integrated circuits so that individual elements can perfectly independently operate.
Methods for forming element isolation regions include the well-known trench isolation method, for which many improvements have been suggested. In the trench isolation, trenches are formed in a substrate and filled with insulation. Since the trench isolation is almost free from bird""s beaks, it is an isolation method indispensable for miniaturization of semiconductor integrated circuits.
A conventional semiconductor device 500 is now described referring to the cross-sectional view of FIG. 63. The semiconductor device 500 has a silicon substrate 501, trench-type element isolation structures 531, and MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) 590.
Trenches 502 are formed into the substrate 501 from the substrate""s main surface 501S and element isolation structures 531 are disposed inside the trenches 502. The conventional element isolation structure 531 is formed of a silicon oxide film or an inner-wall oxide film 531a and a silicon oxide film or a buried oxide film 531b. The inner-wall oxide film 531a is formed along the inner surface of the trench 502 and is entirely in contact with this inner surface. The buried oxide film 531b resides in contact with the inner-wall oxide film 531a to fill the trench 502.
MOSFETs 590 are formed in the active regions or element formation regions that are sectioned by the element isolation structures 531. More specifically, in an active region, a pair of source/drain regions 593 are formed in the substrate""s main surface 501S, with a channel region interposed therebetween, and a gate insulating film 592 of silicon oxide and a gate electrode 591 are formed in this order on the substrate""s main surface 501S or above the channel region.
Next, a method for manufacturing the conventional semiconductor device 500 is now described referring to the cross-sectional views of FIGS. 64 to 67. First, an underlying silicon oxide film 505 and a silicon nitride film 506 are formed in this order on the substrate""s main surface 501S (see FIG. 64). Then the films 505, 506 and the substrate 501 are pattern-etched by photolithography to form the trenches 502 in the substrate 501 (see FIG. 64).
Next, the inner surfaces of the substrate 501 that are exposed within the trenches 502 are thermally oxidized to form the inner-wall oxide film 531a (see FIG. 65). Subsequently, the buried oxide film 531b is deposited over the entire surface by CVD (Chemical Vapor Deposition) method so that the trenches 502 are filled with the buried oxide film 531b (see FIG. 65).
Then the portion of the buried oxide film 531b above the silicon nitride film 506 is removed by CMP (Chemical Mechanical Polishing) method using the silicon nitride film 506 as a stopper, so as to make the buried oxide film 531b flat (see FIG. 66). Subsequently, the buried oxide film 531b is partially removed with hydrofluoric acid (HF) to adjust the height of the element isolation structures 531. Then the silicon nitride film 506 is removed with thermal phosphoric acid and the underlying silicon oxide film 505 is removed with hydrofluoric acid. The element isolation structures 531 are thus completed (see FIG. 67).
The MOSFETs 590 are formed after that. Specifically, wells, channel-cut regions, and channel impurity layers for controlling the threshold are formed by ion implantation, which is followed by the formation of the gate insulating film 592, gate electrodes 591, and source/drain regions 593. The semiconductor device 500 shown in FIG. 63 is thus completed.
A technique about trench isolation is described in the following patent specification 1, for example.
Patent Specification 1: Japanese Patent Application Laid-Open No. 2000-332099.
In the manufacturing method of the semiconductor device 500 shown above, the buried oxide film 531b is deposited in the trenches 502 by CVD. Accordingly, voids are likely to form in the buried oxide film 531b as the aspect ratio of the trenches 502 becomes larger with miniaturization of the semiconductor device 500. Such voids appear as fine grooves in the surfaces of the element isolation structures 531 after the CMP or after the HF treatment of the silicon oxide film 531b and/or 505. When interconnection layer material, for example, is buried in these fine grooves and it remains after the interconnection material has been patterned, then the interconnection layer will be short-circuited. The formation of voids thus reduces the yield.
The void formation can be effectively suppressed by forming the buried oxide film 531b with a silicon oxide film that is doped with impurities and has an improved property to completely fill trenches without voids. However, by thermal process following the formation of the buried oxide film 531b, impurities in the buried oxide film 531b will diffuse into the substrate 501 or an interconnection layer on the element isolation structures 531, causing problems such as variations of characteristics of the MOSFETs 590. Specifically, impurities diffused into the interfaces between the element isolation structures 531 and the substrate 501 or into the substrate 501 will vary the threshold voltage of the MOSFETs 590 or vary the oxidation rate during the formation of the gate insulating film 592. Moreover, when impurities diffused into the substrate 501 form an interface energy state at the interface between the substrate 501 and the gate insulating film 592, then characteristics of the MOSFETs 590 may vary or leakage current may increase. Also, when the impurities diffuse into the gate electrodes 591 extending on the element isolation structures 531, then the work function of the gate electrodes 591 will vary to vary characteristics of the MOSFETs 590.
The above-mentioned patent specification 1 (Japanese Patent Application Laid-Open No. 2000-332099) discloses a technique for suppressing such impurity diffusion by forming a two-layered inner-wall structure, where a silicon nitride film is deposited between the inner-wall oxide film 531a and the buried oxide film 531b. However, depositing a silicon nitride film enlarges the aspect ratio of the trenches 502, and then voids are likely to form during the formation of the buried oxide film 531b. Moreover, silicon nitride film, which suppresses oxidation during the formation of the gate oxide film 592, causes the gate insulating film 592 to form thinner near the element isolation structures 531, which lowers the reliability of the gate insulating film 592.
The present invention has been made in consideration of the problems shown above, and an object of the invention is to provide a semiconductor device that can simultaneously solve problems related to the element isolation, i.e. formation of voids, impurity diffusion from a doped insulator into the semiconductor substrate etc., and thickness reduction of the gate insulating film caused by silicon nitride film.
According to a first aspect of the invention, a semiconductor device includes a semiconductor substrate, a doped insulator doped with impurities, an undoped insulator which is not doped with impurities, a first oxynitride film, and an MIS-type transistor. The semiconductor substrate has a main surface and a trench whose entrance is formed in the main surface. The doped insulator is disposed in the trench. The undoped insulator is disposed in the trench and positioned opposite to the bottom surface of the trench with the doped insulator interposed therebetween. The first oxynitride film is disposed in the trench between the doped insulator and the semiconductor substrate and between the undoped insulator and the semiconductor substrate. The MIS-type transistor is disposed in an area on the main surface of the semiconductor substrate where the trench is absent. The doped insulator is isolated from the semiconductor substrate by the undoped insulator and the first oxynitride film.
According to a second aspect of the invention, a semiconductor device includes a semiconductor substrate, a doped insulator doped with impurities, an undoped insulator which is not doped with impurities, a silicon oxide film, an oxynitride film, and an MIS-type transistor. The semiconductor substrate has a main surface and a trench whose entrance is formed in the main surface. The doped insulator is disposed in the trench. The undoped insulator is disposed in the trench and positioned opposite to the bottom surface of the trench with the doped insulator interposed therebetween. The silicon oxide film is disposed in the trench between the doped insulator and the semiconductor substrate. The oxynitride film is disposed in the trench between the undoped insulator and the semiconductor substrate and between the undoped insulator and the doped insulator. The MIS-type transistor is disposed in an area on the main surface of the semiconductor substrate where the trench is absent. The doped insulator is isolated from the semiconductor substrate by the silicon oxide film, the undoped insulator, and the oxynitride film.
The doped insulator has an improved gap-filling property and can reduce the aspect ratio of the trench, which suppresses formation of voids in the element isolation structure. Moreover, the doped insulator is isolated from the semiconductor substrate by the undoped insulator and the first oxynitride film or by the silicon oxide film, the undoped insulator, and the oxynitride film. It is therefore possible to prevent impurity diffusion from the doped insulator into the semiconductor substrate or into components on the element isolation structure (e.g. gate electrodes). Furthermore, forming the oxynitride film by a nitridation process utilizing the oxide film (e.g. thermal nitridation or plasma nitridation process) avoids a considerable increase of the trench aspect ratio and thus suppresses void formation in the element isolation structure. Also, unlike silicon nitride film, the oxynitride film avoids thickness reduction of the gate insulating film to enhance the reliability of the semiconductor device.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.